1. Field of the Invention
The present invention relates generally to a through silicon via structure and a process thereof, and more specifically to a through silicon via structure and a process thereof that forms a buffer layer between a barrier layer and a conductive layer.
2. Description of the Prior Art
The through-silicon via technique is quite a novel semiconductor technique. The through-silicon via technique advantage mainly resides in solving the problem of the electrical interconnection of chips and the TSV belongs to a new 3D packing technique field. The hot through-silicon via technique creates products that fit better the market trends of “light, thin, short and small” through through-silicon via 3D stacking, to provide the micro electronic mechanic system (MEMS), the photoelectronics and electronic elements with packing techniques of wafer-level package.
The through-silicon via technique drills holes in the wafer through etching or using laser then fills the holes with conductive materials such as copper, polysilicon or tungsten to form vias, i.e. conductive channels connecting inner regions and outer regions. Finally, the wafer or the dice is thinned to be stacked or bonded together to be a 3D stack IC. In this way, the wire bonding procedure maybe omitted. Using etching or laser techniques to form conductive vias not only avoids the wire bonding step but also reduce the occupied area on the circuit board and the volume to be packed.
The inner connection distance of the package of the 3D stack IC with the through-silicon via technique, i.e. the thickness of the thinned wafer or the dice, is much shorter compared to the conventional stack package of wire bonding type, so the 3D stack IC performs better in many ways, for it has smaller electrical resistance, faster transmission, lower noise and better performances. For the CPUs, flash memories and memory cards especially, the advantages of the shorter inner connection distance of the through-silicon via technique are much more outstanding. In addition, the package size of the 3D stack IC equals to the size of the dice, so the through-silicon via technique is more valuable in portable electronic devices.
However, a via of the through-silicon via structure in the wafer formed through etching has a high depth/width ratio, and the depth/diameter ratio of the via can approach 10 times. But a via having a high depth/width ratio formed through etching raise the problem of rough surface of the via. For example, the surface of the via has a scallop cross-sectional profile. The rough surface of the via leads to material layers, such as a seed layer formed thereon, to have a rough surface as well, which degrades the efficiency of the step coverage of the material layers.